In large system-on-a-chip (“SoC”) designs debugging the effects of power intent when using the Liberty format (i.e., .lib) is very difficult. The .lib file is an ASCII representation of the timing and power parameters associated with any cell in a particular semiconductor technology. The timing and power parameters may be obtained by simulating the cells under a variety of. conditions and the data may be represented in the .lib format. The Liberty description is outside of the HDL description and its effects are difficult to understand. Liberty data is relevant to formal verification and is also spread through the liberty files often with thousands of lines between relevant portions. To fully understand what is going on it is difficult to see this in the file.
The use of Liberty to apply low power intent to a design creates a lot of unknowns in the simulation which are very difficult to understand in the context of the HDL design. A liberty file may include information relevant to verification but it also contains information for downstream backend tools which may add information not relevant to HDL verification. It is this extra information that causes a problem in that the file will have relevant pieces dispersed through the file often with 1000's of lines of information that are not relevant. As such, trying to understand the verification aspects in the file is difficult given the distance between lines in the file.